1. Field of the Invention
The present invention relates to semiconductor devices and, in particular, to an adjustable, self-aligned air gap dielectric for low capacitance wiring in semiconductor devices.
2. Description of Related Art
Because of continuing decreases in size of circuit components in semiconductor chips, there are a number of interconnect wiring challenges facing the technical community over the next few technology generations. Among these challenges is the problem of undesirable capacitance in dielectric materials between circuit wiring. One avenue being pursued to lower interconnect capacitance is by the use of porous dielectrics. However, because these materials generally have reduced mechanical strength and thermal conductivity, it is more difficult to build the chip and dissipate heat during chip operation. Another challenge in the next few technology generations is presented by the expectation that the resistivity of copper wiring will begin to rise as the wire line width starts to approach its electron mean free path. This resistivity rise is exacerbated by surface and interface roughness of the copper. Dual damascene trench and via sidewalls may also intersect the voids in adjacent porous dielectric areas and contribute to the copper resistivity rise.
An additional challenge expected by the 65 nm line width generation is that physical vapor deposition (PVD), or sputtered, barriers will need to be replaced with chemical vapor deposition (CVD) or atomic layer deposition (ALD) barriers to meet ongoing thickness reductions and improved conformality requirements. If the porous low k dielectric material used is an open cell type, i.e., with connected pores, then the CVD or ALD precursors can diffuse into the dielectric and degrade its low k characteristics. Also, depending upon the maximum pore size of the porous low k dielectric material, the thinner liners may not be able to provide continuous coverage to prevent copper diffusion into the adjacent dielectric material. For example, some current porous low k materials still have 200 Å max pore size when the barrier needs to be about 50 Å at the 65 nm technology node.